1. Requirement Definition and Adaptation Assessment:
This phase marks the starting point of the customization process. The chip design team engages in deep collaboration with the client to define all core specifications:
Define all relevant specifications, including functional boundaries, computing power requirements, maximum power consumption, interface types, operating temperature ranges, and security levels.
Conduct process adaptation assessments based on specific application scenarios, and provide optimization recommendations regarding material selection, cost structure, and development cycle.
Finally, produce the formal chip specification document to serve as the development benchmark for the subsequent full lifecycle of the project.
2. System Architecture Design:
Based on the specification document, the architecture engineer constructs the top-level architecture:
Define the overall chip architecture, functional module partitioning, power supply topology, and signal timing constraints.
Determine the selection of core IP cores and the bus interconnect architecture, and define the key optimization directions for performance, area, and power consumption.
Generate comprehensive system design documentation, complete architecture-level simulation verification, and eliminate top-level logic conflicts.
3. Front-End Logic Design:
Translate functional requirements into implementable circuit logic, without involving any physical manufacturing details throughout the process:
Write code using hardware description languages such as Verilog or VHDL to implement the logic of each functional module.
Using EDA tools, we performed thousands of rounds of functional simulations to model operating conditions under extreme scenarios, ensuring that all logic circuits fully comply with the specification requirements at 100%.
Finally, generate the standard netlist file, thereby completing the transformation from code to a logic circuit diagram.
4. Back-End Physical Design:
In this phase, the front-end logic is converted into a manufacturable physical layout suitable for tape-out:
Complete the layout and routing of the chip, strictly adhere to wafer fabrication process rules, and address physical challenges such as signal integrity, power consumption and voltage drop, and thermal management.
Perform timing verification and physical rule checks to ensure that the layout fully complies with the manufacturing constraints of the foundry.
Generate the final GDSII layout file, which is the core production file for chip tape-out.
5. Tape-out, Packaging, and Testing:
Deliver the layout file to the foundry to complete physical chip fabrication:
The foundry completes the full suite of semiconductor manufacturing processes-including wafer photolithography and etching-according to the GDSII specifications, and produces bare chips.
Select the appropriate packaging type (e.g., QFN, BGA, TO-220, etc.) based on the application requirements, and complete the chip packaging process.
Perform comprehensive dimensional testing: ambient temperature functional testing, wide-temperature range stability testing, and full-load durability testing, followed by the rejection of defective products.
6. Mass Production and Delivery:
Upon completing small-batch trial production validation, the process proceeds to the stable mass production phase:
Establish standardized mass-production testing processes to ensure the consistency of batch chips.
Provide synchronous delivery of drivers and development SDKs for the chips, offer ongoing technical support, and assist customers in completing terminal product adaptation.